000 00843nam0a22002170004500
001 76582
005 20200804113600.0
010 _a0-444-89153-6
_b(Encadernado)
090 _a76582
100 _a19931007d1992 k y0pory5003 ba
101 0 _aeng
102 _aNL
200 1 _aAlgorithms and parallel VLSI architectures II
_eproceedings
_fInternational Workshop on Algorithms...
_ged. Patrice Quinton, Yves Robert
210 _aAmsterdam
_cElsevier
_d1992
215 _aXVI, 388 p.
_cil.
_d25 cm
675 _a681.3.02
_vint
_zeng
702 1 _9144995
_aQuinton,
_bPatrice
_4340
702 1 _9150390
_aRobert,
_bYves
_4340
710 1 2 _aInternational Workshop on Algorithms and Parallel VLSI Architectures,
_d2,
_eGers,
_f1991
942 _cLIVRO
_n0